Fundamentals of IP and SoC Security (PDF)

Research Scientist at Strategic CAD Labs, Intel Corporation where he led the research on pre-silicon and post-silicon validation of security and functional correctness of Intel's next-generation SoC designs, design-for-security and design-for-debug architectures, CAD tools, and specifications for security assurance. Dr. Ray has over 60 publications in peer-reviewed premier international journals and conferences.  He was a guest editor for an IEEE Transactions on Multi-Scale Systems (TMSCS) special issue on Wearables, Implants, and Internet-of-Things, as well as special issues of ACM Transactions on Design Automation of Electronic Systems (TODAES) and Springer Journal on Electronic Testing Theory and Applications (JETTA). His research has found applications in a number of companies, including AMD, Freescale, Galois, IBM, Intel, NXP, and Rockwell Collins. He has received several recognition awards from Intel for his extensive contribution in the field of security architecture and validation. He has given invited, tutorial, and keynote presentations at several international forums on security, validation, and energy challenges in the IoT regime. Dr. Ray has served as a program committee member more than 40 international meetings and conferences, and as program chair for Formal Methods in Computer-Aided Design. He currently serves as an Associate Editor for IEEE TMSCS and Springer Journal on Hardware and Systems Security.  He has a Ph.D. from University of Texas at Austin and is a Senior Member of IEEE.


Susmita Sur-Kolay received the B.Tech.(Hons.) degree in Electronics and Electrical Communications Engineering from Indian Institute of Technology Kharagpur and the Ph.D. degree in Computer Science and Engineering from Jadavpur University India. She has been a faculty member in the Advanced Computing and Microelectronics Unit of the Indian Statistical Institute, Kolkata, India since 1999 and is presently a Professor as well as the Professor-in-Charge of the Computer and Communication Sciences Division of the institute. During the period 1993-99, she was a Reader in the Department of Computer Science and Engineering of Jadavpur University. Prior to that, she was a post-doctoral fellow at University of Nebraska-Lincoln, and a Research Assistant at the Laboratory for Computer Science in Massachusetts Institute of Technology. She was also a Visiting Researcher at Princeton University and Visiting Faculty at Intel Corp., USA. Her research contributions are in the areas of electronic design automation for VLSI physical design, fault modeling and testing, hardware security, synthesis of quantum computers, and graph algorithms. She has several international research collaborations.  She has co-edited two books, authored a book chapter in the Handbook of Algorithms for VLSI Physical Design Automation, and co-authored about 100 technical articles in leading international journals and refereed conference proceedings. She was the General Co-Chair of the 29th International Conference on VLSI Design (2016), Technical Program Co-Chair of the 18th International Conference on VLSI Design (2005), the 11th Symposium on VLSI Design and Test (2007), and  ISVLSI 2011, and has served on the program committees of several international conferences. She has served on the editorial board of the IET Computers and Digital Techniques, and IEEE Transactions on VLSI Systems. She is a Distinguished Visitor of IEEE Computer Society (India), Senior Member of IEEE, Member of ACM, IET and VLSI Society of India. Among other awards, she was the recipient of the President of India Gold Medal (summa cum laude) at IIT Kharagpur (1980), IBM Faculty Award (2009).