Dependable Multicore Architectures at Nanoscale (PDF)

on Computers IEEE Transactions on VLSI Systems, IEEE Design & Test of Computers Magazine and currently serves as associate editor in IEEE Transactions on Sustainable Computing and Springer's JETTA. He served several times as member of the Steering, Organizing and Program Committees, and as General and Program Chair of major IEEE and ACM conferences. He is an IEEE Fellow and a Golden Core Member of IEEE Computer Society. He participated in and led several research and development projects funded by the EU, the Greek government and private funds from companies. Gizopoulos is the University of Athens lead in the CLERECO FP7 project and the UniServer H2020 project, and coordinator of the HOLISTIC and DIaSTEMA projects (both funded by EU and the Greek government), a member of HiPEAC NoE and the Vice-chair of the MEDIAN ESF-funded COST Action.

Salvatore Pontarelli received the master Degree at university of Bologna in 2000. In 2003 takes its PhD degree in microelectronics and telecommunications from the University of Rome Tor Vergata. Currently, he works as Senior Hardware Design Engineer at CNIT (Italian Consortium of telecommunication), in the research unit of University of Rome Tor Vergata. His research mainly focuses on error detection and correction codes, arithmetic self checking circuits and reconfigurable architectures. He is also interested in the use of reconfigurable hardware for high speed network monitoring. In the past Dott. Pontarelli has worked with the National Research Council (CNR), the Department of Electronic Engineering of University of Rome Tor Vergata, the Italian Space Agency (ASI), the Univeristy of Bristol and has been consultant for various italian and european companies for projects related to digital design and to fault tolerance in digital systems. He partecipates in several national and EU funded research program (ESA, FP7 and H2020) and in 2011 he has been awarded of the prestigious CISCO research Award fora study on the use of Bloom filter for error detection in Ternary CAM.

He has published more than 90 papers on archival journals (mostly IEEE)and peer-reviewed conferences, and has served as reviewer for many IEEE sponsored journals and conferences. He has been general chair of the second MEDIAN Workshop, Program chair of the IEEE Symposium on Defect and Fault Tolerance in VLSI systems, in 2014 and he is General chair of the IEEE Symposium on Defect and Fault Tolerance in VLSI systems in 2015. He has been Guest Editor for: Embedded Hardware Design Journal - Microprocessors and Microsystems, IEEE Transactions on Computers, IEEE Transactions on nanotechnology. He is Associate Editor for IEEE Transactions on nanotechnology for the years 2015-16.