VLSI Design and Test

newactive block.- Highly Non-linear Feed-Forward Arbiter PUF against Machine Learning Attacks.- An Online Testing Technique for the Detection of Control Nodes Displacement Faults (CNDF) in Reversible Circuits.- An Approach towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array.- Digital Design.- MANA: Multi-Application Mapping onto Mesh Network-on-Chip using ANN.- Metastable SR Flip-Flop based True Random Number Generator using QCA Technology.- Hardware Design of Two Stage Reference Free Adaptive Filter for ECG Denoising.- A Reconfigurable Arbiter PUF based on VGSOT MTJ.- Pass Transistor XOR Gate based Radiation Hardened RO-PUF.- QCA Technology based 8-bit TRNG Design for Cryptography Applications.- Signal Integrity and Power Loss Analysis for different Bump Structures in Cylindrical TSV.- Reliability Aware Global Routing of Graphene Nanoribbon Based Interconnect.- Low Cost Hardware Design of ECCScalar Multiplication.- Scalable Construction of Formal Error Guaranteed LUT-based Approximate Multipliers with Analytical Worst-Case Error Bound.- Design of a Programmable Delay Line with On-Chip Calibration to Achieve Immunity against Process Variations.- High Performance Ternary Full Adder in CNFET-Memristor Technology.- Synthesis of LUT based Approximating Adder Circuits with Formal Error Guarantees.- Emerging Technologies and Memory.- CAR: Community Aware Graph Reordering for Efficient Cache Utilization in Graph Analytics.- Indigenous Fab-Lab Hybrid Device Integration for Phase Change Memory for In-Memory Computing.- Resistive switching behavior of TiO2/(PVP:MoS2) nanocomposite bilayer hybrid RRAM.- RTQCC-14T: Radiation Tolerant Quadruple Cross Coupled Robust SRAM Design for Radiation Prone Environments.- Disrupting Low-write-energy vs. Fast-read Dilemma in RRAM to Enable L1 Instruction Cache.- System Design.- Implementation and Analysis of Convolution Image Filtering with RISC-V Based Architecture.- Development of Distributed Controller for Electronic Beam Steering using Indigenous Rad-Hard ASIC.- Tile Serial Protocol (TSP) ASIC for Distributed Controllers of Space-borne Radar.- A deep dive into CORDIC Architectures to implement trigonometric functions.- Impact of Operand Ordering in Approximate Multiplication in Neural Network and Image Processing Applications.- An Overlap-and-Add based Time-domain Acceleration of CNNs on FPGA-CPU Systems.- Low Cost Implementation of Deep Neural Network On Hardware.