Low-Power High-Speed Adcs for Nanometer CMOS Integration

Name: Low-Power High-Speed Adcs for Nanometer CMOS Integration
Brand: Springer Netherland, SPRINGER NATURE
SKU: 19206648
Price: 224.90 CHF
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(Sprache: Englisch)

Autoren: Zhiheng Cao , Shouli Yan

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Low-Power High-Speed Adcs for Nanometer CMOS Integration, Zhiheng Cao, Shouli Yan

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This text is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes.

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Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input.

Inhaltsverzeichnis zu „Low-Power High-Speed Adcs for Nanometer CMOS Integration “

Preface. List of Tables. List of Figures. 1. Introduction. 1 Motivations. 2 A Review of Existing ADC Architectures.2. A 52mW 10b 210MS/s Two-Step ADC for Digital IF Receivers in 130nm CMOS. 1 Background. 2 Architecture and Circuits. 3 Experimental Results. 4 Summary.3. A 32mW 1.25GS/s 6b 2b/Step SAR ADC in 130nm Digital CMOS 47. 1 Background. 2 Architecture. 3 Enabling Circuits. 4 Testing Issues. 5 Experimental Results. 6 Performance Summary and Comparison. 7 Summary.4. A 0.4ps-RMS-Jitter 1-3GHz Clock Multiplier PLL Using Phase-Noise Preamplification. 1 Introduction. 2 Phase-Lock Loop (PLL). 3 VCO and Clock Buffers. 4 Experimental Results. 5 Summary.5. Conclusions and Future Directions. References. About the Authors.

Bibliographische Angaben

Autoren: Zhiheng Cao , Shouli Yan
2008, 95 Seiten, Masse: 16,7 x 24,4 cm, Gebunden, Englisch
Verlag: Springer Netherland
ISBN-10: 1402084498
ISBN-13: 9781402084492

Sprache:

Englisch

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