Algorithms and Architectures for Parallel Processing

Analytical Modeling for Multi-transaction Bus on Distributed Systems.- Leveraging the Strengths of Transactional Memory While Maintaining System Performance for a Multiplayer Gaming.- Enhancing the Performance of a Distributed Mobile Computing Environment by Topology Construction.- Frame Error Rate Testing for High Speed Optical.- Maintaining Consistency in Software Transactional Memory through Dynamic Versioning Tuning.- Solving a 2-Covered Path Problem with Variable Radii for Wireless Sensor Networks.- Design of an Application-Dependent Static-Based Shared Memory Network.- Determining Quality of S-Boxes Using Pseudo Random Sequences Generated from Stream Ciphers.- Exploring Object-Level Parallelism on Chip Multi-processors.- The Hamiltonicity of WK-Recursive Pyramid.- Towards Multi-level Adaptation for Distributed Operating Systems and Applications.- FIDs Classifier for Artificial Intelligence and Its.- On Affirmative Adaptive Failure Detection.- A New Low Latency Parallel Turbo Decoder Employing Parallel Phase Decoding Method.- A Regular Group Quorum System of Degree A Note on Developing Optimal and Scalable Parallel Two-List Algorithms.- Small Business-Oriented Index Construction of Cloud Data.- High-Performance Matrix Multiply on a Massively Multithreaded Fiteng1000 Processor.- BIDE-Based Parallel Mining of Frequent Closed Sequences with MapReduce.- Efficient Task Scheduling for Hard Real-Time Tasks in Asymmetric Multicore Processors.- An Implementation of Parallel 2-D FFT Using Intel AVX Instructions on Multi-core Processors.- A Semantic Impact in Decentralized Resource Discovery Mechanism for Grid Computing Environments.- Design of n-Gram Based Dynamic Pre-fetching for DSM.- On Construction of Cloud IaaS for VM Live Migration Using KVM and OpenNebula.- Performance Evaluation of OpenMP and CUDA on Multicore.- Complexity of the Resource Allocation/Matching Problem with Weight Based Ceilings.- Wireless SensorNetwork Internal Attacker Identification with Multiple

Ivan Stojmenovic, PhD, is a researcher in DISCA, IIMAS, UNAM, Mexico, and a professor in the School of Information Technology and Engineering at the University of Ottawa, Canada. He is a managing editor of Multiple-Valued Logic and an editor of several journals. He has also published more than 150 academic papers.