Proceedings of the Fourth International Conference on Microelectronics, Computing and Communication Systems

Diode Switch based 17-level inverter with lesser power electronic elements.- 28GHz 5G Receiver Design using 65nm CMOS and Performance Analysis through Simulation.- Study and implementation of ladder logic conversion to VHDL for Field programmable gate array (FPGA) based Programmable Logic Controllers (PLC).- Automated Monitoring and Regulation of User Friendly Greenhouse using Arduino.- An Involution Function Based Symmetric Stream Cipher.- Multi-Objective Optimization of Block Size based on CPU Power & Network Bandwidth for Blockchain Applications

Dr. Vijay Nath was born in Gorakhpur (U.P.) India in 1976. He received his bachelor's degree in Physics and master's degree in Electronics from DDU Gorakhpur University, India, in 1998 and 2001. He also received PGDCN (GM) from MMMUT Gorakhpur in 1999. He received his Ph.D. degree in VLSI Design & Technology from Dr. RML Avadh University Faizabad in association with CEERI, Pilani, in 2008. From 2000 to 2001, he served as project trainee in IC Design Group, CEERI, Pilani, under the guidance of Dr. K.S.Yadav (Senior Scientist). From 2002 to 2006, he severed as Faculty in the Department of Electronics, DDU University Gorakhpur. Presently, he is an Associate Professor in the Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi (JH), India, and joined this institute in 2006. He has academic and administrative responsibilities such as Professor In-charge of Embedded System Design Lab, Advisor of NAPS (News & Publication Society), member of BIT Mesra Brand Management, Faculty Advisor IEI Student Chapter (ECE) BIT Mesra and Honorary Secretary of IETE Ranchi Centre. He is the recipient of Viveka Nanda Techno Fiesta Award-2002, Young Scientist Award-2004, CCSN Best Paper Award-2013, First Prize in IEI Technical Contest-2013 and Cadence Design Contest-2014, 2016. His research interests include microelectronics, nanoelectronics, analog, digital, mixed CMOS VLSI circuits, low-power VLSI circuits, ultra-low-power CMOS temperature sensor, ADC, DAC, PTAT, CMOS bandgap voltage reference, ASICs, embedded systems designs, smart cardiac pacemaker, smart grids, Internet of things and early stage cancer detection. He has to his credit around 150 publications in reputed Scopus & SCI journals, Scopus books and conferences. He has successfully completed two R&D projects funded by DST New Delhi jointly with DRDL Hyderabad and MHRD New Delhi, and the third project is in ongoing stage funded by RESPOND SAC ISRO Ahmadabad,