Model and Design of Improved Current Mode Logic Gates
Differential and Single-ended
(Sprache: Englisch)
This book presents MOSFET-based current mode logic (CML) topologies, which increase the speed, and lower the transistor count, supply voltage and power consumption. The improved topologies modify the conventional PDN, load, and the current source sections...
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This book presents MOSFET-based current mode logic (CML) topologies, which increase the speed, and lower the transistor count, supply voltage and power consumption. The improved topologies modify the conventional PDN, load, and the current source sections of the basic CML gates.Electronic system implementation involves embedding digital and analog circuits on a single die shifting towards mixed-mode circuit design. The high-resolution, low-power and low-voltage analog circuits are combined with high-frequency complex digital circuits, and the conventional static CMOS logic generates large current spikes during the switching (also referred to as digital switching noise), which degrade the resolution of the sensitive analog circuits via supply line and substrate coupling. This problem is exacerbated further with scaling down of CMOS technology due to higher integration levels and operating frequencies. In the literature, several methods are described to reduce the propagation of the digital switching noise. However, in high-resolution applications, these methods are not sufficient. The conventional CMOS static logic is no longer an effective solution, and therefore an alternative with reduced current spikes or that draws a constant supply current must be selected. The current mode logic (CML) topology, with its unique property of requiring constant supply current, is a promising alternative to the conventional CMOS static logic.
Inhaltsverzeichnis zu „Model and Design of Improved Current Mode Logic Gates “
CHAPTER 1 INTRODUCTION1.1Background1.2Available Literature 1.2.1Various CML topologies1.2.2Modeling and Design Approaches1.2.3System Application1.3Organization of the Book
CHAPTER 2 CML GATES: BASIC CONCEPTS
2.1Introduction2.2Basic Concepts2.3Differential CML Gates2.3.1Operation of the differential CML inverter 2.3.2Analysis of the differential CML inverter 2.3.2.1Static model2.3.2.2Delay model2.3.3Design of the differential CML inverter2.3.4Realization of the basic gates2.4Single-ended CML Gates2.4.1Operation of the PFSCL inverter 2.4.2Analysis of the PFSCL inverter 2.4.2.1Static model2.4.2.2Delay model2.4.3Design of the PFSCL inverter2.4.4Realization of the basic gates2.5Concluding Remarks
CHAPTER 3DIFFERENTIAL CML GATES WITH MODIFIED PDN
3.1Introduction3.2Literature Survey3.3New Appraoch3.4Improved Combinational Gates with Modified PDN3.4.1 Operation of the improved XOR gate3.4.2Analysis of the improved XOR gate3.4.2.1Static model3.4.2.2Delay model3.4.3Design of the improved XOR gate3.4.4Performance comparison3.4.4.1High speed design3.4.4.2Power efficient design3.4.4.3Low power design3.5Improved Sequential Gates with Modified PDN 3.5.1Operation of the improved D latch3.5.2Analysis of the improved D latch 3.5.2.1Static model3.5.2.2Delay model3.5.3Design of the improved D latch3.5.4Performance comparison3.5.4.1High speed design3.5.4.2Power efficient design3.5.4.3Low power design3.6Concluding Remarks
CHAPTER 4CML GATES WITH MODIFIED CURRENT SOURCE
4.1Introduction4.2Survey of the Current Source Modifications4.3 Dynamic Current Source4.3.1Existing NN-dynamic current source4.3.2 New NP-dynamic current source4.4 Improved Differential CML Gates with NP-dynamic current source4.4.1 Operation of the D-MCML-NP inverter4.4.2 Design of the D-MCML-NP inverter4.4.3 Power consumption analysis4.5 Improved PFSCL Gates with NN-dynamic current source4.5.1 Operation of the D-PFSCL-NN
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inverter4.5.2 Design of the D-PFSCL-NN inverter4.5.3Power consumption analysis4.6Improved PFSCL Gates with NP- dynamic current source4.6.1 Operation of the D-PFSCL-NP inverter4.6.2 Design of the D-PFSCL-NP inverter4.6.3 Power consumption analysis4.7Multi-stage Applications4.7.1 Existing self-timed buffer4.7.2 Improved self-timed buffer4.8Performance Comparison4.8.1Performance comparison of the differential D-CML gates4.8.2Performance comparison of the D-PFSCL gates4.9Concluding Remarks
CHAPTER 5CML GATES WITH MODIFIED LOAD
5.1Introduction5.2Available Loads5.3New load (NP-Load)5.3.1Analysis of the NP-load5.3.2 Resistance of the NP-load5.4Improved Differential CML Gates with Modified Load5.4.1 Operation of the MCML-CC inverter5.4.2 Analysis of the MCML-CC inverter5.4.2.1Static model5.4.1.1Delay model5.4.3Design of the MCML-CC inverter5.4.4Performance comparison5.5 Improved PFSCL Gates with Modified Load5.5.1 Operation of the PFSCL-CC inverter5.5.2 Analysis of the PFSCL-CC inverter5.5.2.1Static model5.5.2.2Delay model5.5.3 Design of the PFSCL-CC inverter5.5.4 Performance comparison5.6 Concluding Remarks
CHAPTER 6PFSCL CIRCUITS WITH REDUCED GATE COUNT
6.1Introduction6.2Existing Realization of PFSCL circuits6.3New Realization of PFSCL circuits6.3.1New fundamental cell6.3.1.1 Architecture and operation6.3.1.2 Analysis of the fundamental cell 6.3.2 Improved Realization of the PFSCL circuits6.3.3 Performance comparison6.4Concluding Remarks
CHAPTER 7TRI-STATE CML CIRCUITS
7.1Introduction7.2Literature Survey on Tri-state CML Circuits7.2.1Switch based tri-state CML circuit7.2.2Voltage follower based tri-state CML circuit7.3Improved Differential Tri-state CML circuit 7.3.1Operation of the circuit7.3.2Performance comparison7.3.3Application examples7.4Concluding Remarks
REFERENCES
CHAPTER 5CML GATES WITH MODIFIED LOAD
5.1Introduction5.2Available Loads5.3New load (NP-Load)5.3.1Analysis of the NP-load5.3.2 Resistance of the NP-load5.4Improved Differential CML Gates with Modified Load5.4.1 Operation of the MCML-CC inverter5.4.2 Analysis of the MCML-CC inverter5.4.2.1Static model5.4.1.1Delay model5.4.3Design of the MCML-CC inverter5.4.4Performance comparison5.5 Improved PFSCL Gates with Modified Load5.5.1 Operation of the PFSCL-CC inverter5.5.2 Analysis of the PFSCL-CC inverter5.5.2.1Static model5.5.2.2Delay model5.5.3 Design of the PFSCL-CC inverter5.5.4 Performance comparison5.6 Concluding Remarks
CHAPTER 6PFSCL CIRCUITS WITH REDUCED GATE COUNT
6.1Introduction6.2Existing Realization of PFSCL circuits6.3New Realization of PFSCL circuits6.3.1New fundamental cell6.3.1.1 Architecture and operation6.3.1.2 Analysis of the fundamental cell 6.3.2 Improved Realization of the PFSCL circuits6.3.3 Performance comparison6.4Concluding Remarks
CHAPTER 7TRI-STATE CML CIRCUITS
7.1Introduction7.2Literature Survey on Tri-state CML Circuits7.2.1Switch based tri-state CML circuit7.2.2Voltage follower based tri-state CML circuit7.3Improved Differential Tri-state CML circuit 7.3.1Operation of the circuit7.3.2Performance comparison7.3.3Application examples7.4Concluding Remarks
REFERENCES
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Autoren-Porträt von Kirti Gupta, Neeta Pandey, Maneesha Gupta
Dr. Kirti Gupta received B.Tech. in Electronics and Communication Engineering from Indira Gandhi Institute of Technology, Delhi in 2002, M. Tech. in Information Technology from School of Information Technology in 2006. She received her Ph.D. in Electronics and Communication Engineering from Delhi Technological University, in 2016. Since 2002, she is with Bharati Vidyapeeth's College of Engineering, New Delhi and is presently serving as Professor in the same institute. A life member of ISTE, and senior member of IEEE, she has published more than 100 research papers in international, national journals and conferences. Her teaching and research interest is in digital VLSI design. Dr. Neeta Pandey received her M.E. in Microelectronics from Birla Institute of Technology and Sciences, Pilani in 1991 and Ph.D. from Guru Gobind Singh Indraprastha University, Delhi in 2009. She has served in Central Electronics Engineering Research Institute, Pilani, Indian Institute of Technology, Delhi, Priyadarshini College of Computer Science, Noida and Bharati Vidyapeeth's College of Engineering, Delhi in various capacities. At present, she is a professor in the ECE department, Delhi Technological University. Her teaching and research interests include analog and digital VLSI design.
A life member of ISTE, and senior member of IEEE, USA, she has coauthored over 100 papers in international, national journals of repute and conferences.
Dr. Maneesha Gupta is currently a Professor at the Electronics & Communication Engineering Department of the Netaji Subhas University of Technology, India. She received her B.E. in Electronics & Communication Engineering from the Government Engineering College, Jabalpur in 1981, M.E. in Electronics & Communication Engineering from the same university in 1983, and her PhD. in Electronics Engineering (Analysis, Synthesis & Applications of Switched Capacitor Circuits) from the Indian
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Institute of Technology, Delhi in 1990.
Her teaching and research interests include switched capacitor circuits and analog signal processing. Dr. Gupta has co-authored over 150 research papers in the above areas in various international/national journals and conferences.
Her teaching and research interests include switched capacitor circuits and analog signal processing. Dr. Gupta has co-authored over 150 research papers in the above areas in various international/national journals and conferences.
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Bibliographische Angaben
- Autoren: Kirti Gupta , Neeta Pandey , Maneesha Gupta
- 2020, 1st ed. 2020, XIV, 171 Seiten, 2 farbige Abbildungen, Masse: 15,7 x 23,7 cm, Kartoniert (TB), Englisch
- Verlag: Springer, Berlin
- ISBN-10: 9811509840
- ISBN-13: 9789811509841
Sprache:
Englisch
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