Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
(Sprache: Englisch)
This book presents fresh research techniques, algorithms, methodologies and experimental results for high-level power estimation and power-aware high-level synthesis. The book will help get products to market quicker and facilitate low-power ASIC/FPGA design.
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Produktinformationen zu „Low Power Design with High-Level Power Estimation and Power-Aware Synthesis “
This book presents fresh research techniques, algorithms, methodologies and experimental results for high-level power estimation and power-aware high-level synthesis. The book will help get products to market quicker and facilitate low-power ASIC/FPGA design.
Klappentext zu „Low Power Design with High-Level Power Estimation and Power-Aware Synthesis “
This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.
Inhaltsverzeichnis zu „Low Power Design with High-Level Power Estimation and Power-Aware Synthesis “
Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.Bibliographische Angaben
- Autoren: Sumit Ahuja , Avinash Lakshminarayana , Sandeep Kumar Shukla
- 2012, 2012, XXII, 170 Seiten, Masse: 15,4 x 23,6 cm, Kartoniert (TB), Englisch
- Verlag: Springer, Berlin
- ISBN-10: 1489987800
- ISBN-13: 9781489987808
Sprache:
Englisch
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