Low-Noise Low-Power Design for Phase-Locked Loops
Multi-Phase High-Performance Oscillators
(Sprache: Englisch)
This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for...
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This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.
Inhaltsverzeichnis zu „Low-Noise Low-Power Design for Phase-Locked Loops “
Introduction.- Analysis of Quantization Noise Reduction Techniques for Fractional-N PLL.- A Wide-Band 0.13µm SiGe BiCMOS PLL for X-Band Radar.- Design and Analysis of QVCO with Different Coupling Techniques.- Design and Analysis of a 0.6V QVCO with Capacitive-Coupling Technique.- Conclusions.Bibliographische Angaben
- Autoren: Feng Zhao , Fa Foster Dai
- 2016, Softcover reprint of the original 1st ed. 2015, XIII, 96 Seiten, 24 farbige Abbildungen, Masse: 15,5 x 23,5 cm, Kartoniert (TB), Englisch
- Verlag: Springer, Berlin
- ISBN-10: 331934370X
- ISBN-13: 9783319343709
Sprache:
Englisch
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