High Performance Multi-Channel High-Speed I/O Circuits
(Sprache: Englisch)
This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation...
Voraussichtlich lieferbar in 3 Tag(en)
versandkostenfrei
Buch (Kartoniert)
Fr. 118.00
inkl. MwSt.
- Kreditkarte, Paypal, Rechnungskauf
- 30 Tage Widerrufsrecht
Produktdetails
Produktinformationen zu „High Performance Multi-Channel High-Speed I/O Circuits “
Klappentext zu „High Performance Multi-Channel High-Speed I/O Circuits “
This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures.
Inhaltsverzeichnis zu „High Performance Multi-Channel High-Speed I/O Circuits “
Introduction.- 2x6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process.- 4x12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process.- Adaptive XTCR, AGC, and Adaptive DFE Loop.- Research Summary & Contributions.- References.- Appendix A: Noise Analysis.- Appendix B: Issues of Applying Consecutive 2x2 XTCR on Multi-Lane I/Os ( 4).- Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter versus Receiver-Side Analog-IIR XTC Filter.- Appendix D: Line Mismatch Sensitivity.- Appendix E: Input Matching for 4x4 XTCR Receiver Test Bench.- Appendix F: Bandwidth Improvement by Technology Scaling.
Bibliographische Angaben
- Autoren: Taehyoun Oh , Ramesh Harjani
- 2016, Softcover reprint of the original 1st ed. 2014, X, 89 Seiten, 44 farbige Abbildungen, Masse: 15,7 x 23,4 cm, Kartoniert (TB), Englisch
- Verlag: Springer, Berlin
- ISBN-10: 1493954229
- ISBN-13: 9781493954223
Sprache:
Englisch
Kommentar zu "High Performance Multi-Channel High-Speed I/O Circuits"
0 Gebrauchte Artikel zu „High Performance Multi-Channel High-Speed I/O Circuits“
| Zustand | Preis | Porto | Zahlung | Verkäufer | Rating |
|---|
Schreiben Sie einen Kommentar zu "High Performance Multi-Channel High-Speed I/O Circuits".
Kommentar verfassen