Enhanced Virtual Prototyping

Introduction.- Preliminaries.- An Open-Source RISC-V Evaluation Platform.- Formal Verification of SystemC-based Designs using Symbolic Simulation.- Coverage-guided Testing for Scalable Virtual Prototype Verification.- Verification of Embedded Software Binaries using Virtual Prototypes.- Validation of Firmware-Based Power Management using Virtual Prototypes.- Register-Transfer Level Correspondence Analysis.- Conclusion.- Index

Vladimir Herdt received the M.Sc. degree in computer science from the University of Bremen, Germany, in 2014. Afterwards, he started as a PhD student with the Group of Computer Architecture. In 2020, he received the Dr.-Ing. degree in computer science from the University of Bremen. Since 2020, he is Senior Researcher at the Cyber-Physical Systems department of the German Research Center for Artificial Intelligence (DFKI). His current research interests include virtual prototyping as well as verification and analysis techniques with a particular focus on RISC-V. In these areas he published more than 25 peer-reviewed journal and conference papers. He is recipient of the Springer BestMasters award. 




Daniel Grosse received the Dr.-Ing. degree in computer science from the University of Bremen in 2008. He remained as a Post-Doctoral Researcher with the Group of Computer Architecture, University of Bremen. In 2010, he was a substitute Professor for computer architecture with Albert-Ludwigs University, Freiburg im Breisgau, Germany. From 2013 to 2014, he was the CEO of the EDA start-up solvertec focusing on automated debugging techniques. Since 2015, he has been a Senior Researcher with the University of Bremen and at the German Research Center for Artificial Intelligence (DFKI), and also the Scientific Coordinator of the Graduate School of System Design, funded within the German Excellence Initiative. Since July 2020, he is a full professor at the Johannes Kepler University Linz, Austria, where he is the head of the group from Complex Systems. His current research interests include verification, virtual prototyping, debugging, and synthesis. He published over 130 papers in peer-reviewed journals and conferences in the above areas. Dr. Grosse served in program committees of numerous conferences, including DAC, DATE, ICCAD, CODES+ISSS, FDL, and MEMOCODE. He received best paper awards at FDL 2007, DVCon Europe 2018, and ICCAD 2018. He is an IEEE