Nano-CMOS Circuit and Physical Design / Wiley - IEEE (PDF)

FOREWORD. PREFACE. 1 NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS. 1.1 Design Methodology in the Nano-CMOS Era. 1.2 Innovations Needed to Continue Performance Scaling. 1.3 Overview of Sub-100-nm Scaling Challenges and Subwavelength Optical Lithography. 1.4 Process Control and Reliability. 1.5 Lithographic Issues and Mask Data Explosion. 1.6 New Breed of Circuit and Physical Design Engineers. 1.7 Modeling Challenges. 1.8 Need for Design Methodology Changes. 1.9 Summary. References. PART I: PROCESS TECHNOLOGY AND SUBWAVELENGTH OPTICAL LITHOGRAPHY: PHYSICS, THEORY OF OPERATION, ISSUES, AND SOLUTIONS. 2 CMOS DEVICE AND PROCESS TECHNOLOGY. 2.1 Equipment Requirements for Front-End Processing. 2.2 Front-End-Device Problems in CMOS Scaling. 2.3 Back-End-of-Line Technology. References. 3 THEORY AND PRACTICALITIES OF SUBWAVELENGTH OPTICAL LITHOGRAPHY. 3.1 Introduction and Simple Imaging Theory. 3.2 Challenges for the 100-nm Node. 3.3 Resolution Enhancement Techniques: Physics. 3.4 Physical Design Style Impact on RET and OPC Complexity. 3.5 The Road Ahead: Future Lithographic Technologies. References. PART II: PROCESS SCALING IMPACT ON DESIGN 4 MIXED-SIGNAL CIRCUIT DESIGN. 4.1 Introduction. 4.2 Design Considerations. 4.3 Device Modeling. 4.4 Passive Components. 4.5 Design Methodology. 4.6 Low-Voltage Techniques. 4.7 Design Procedures. 4.8 Electrostatic Discharge Protection. 4.9 Noise Isolation. 4.10 Decoupling. 4.11 Power Busing. 4.12 Integration Problems. 4.13 Summary. References. 5 ELECTROSTATIC DISCHARGE PROTECTION DESIGN. 5.1 Introduction. 5.2 ESD Standards and Models. 5.3 ESD Protection Design. 5.4 Low-C ESD Protection Design for High-Speed I/O. 5.5 ESD Protection Design for Mixed-Voltage I/O. 5.6 SCR Devices for ESD Protection. 5.7 Summary. References. 6 INPUT/OUTPUT DESIGN. 6.1 Introduction. 6.2 I/O Standards. 6.3 Signal Transfer. 6.4 ESD Protection. 6.5 I/O Switching Noise. 6.6 Termination. 6.7 Impedance Matching. 6.8 Preemphasis. 6.9 Equalization. 6.10 Conclusion.

BAN P. WONG, IENG MIEE, served for five years as a member of the technical program committee of IEEE International Solid-State Circuits Conference and as session chair, cochair, and organizer of a panel session. He has three issued patents. He has led circuit design teams in developing methodology and implementation of high-performance and low-power microprocessors. He is currently Senior Engineering Manager for NVIDIA Corporation.

ANURAG MITTAL received his PhD in applied physics from Yale University. He has codeveloped novel embedded NVM microcontroller and microprocessor solutions including the world's first truly CMOS-compatible Flash technology. He is Senior Staff Engineer for Virage Logic, Inc.

YU CAO received his PhD in electrical engineering from University of California, Berkeley. He is a postdoctoral researcher in the Berkeley Wireless Research Center. He received the 2000 Beatrice Winner Award at the IEEE International Solid-State Circuits Conference.

GREG STARR received his PhD in electrical engineering from Arizona State University. Currently, he is a Senior Design Manager at Xilinx Corporation.

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