VLSI Physical Design
from Graph Partitioning to Timing Closure
(Sprache: Englisch)
LSI Physical Design explores how algorthims can be used to create a geometric chip layout can be created from an abstract circuit design. The text emphasizes essential, fundamental techniques, ranging from hypergraph partictioning and circuit placement to timing closure.
Leider schon ausverkauft
versandkostenfrei
Buch (Gebunden)
Fr. 160.90
inkl. MwSt.
- Kreditkarte, Paypal, Rechnungskauf
- 30 Tage Widerrufsrecht
Produktdetails
Produktinformationen zu „VLSI Physical Design “
LSI Physical Design explores how algorthims can be used to create a geometric chip layout can be created from an abstract circuit design. The text emphasizes essential, fundamental techniques, ranging from hypergraph partictioning and circuit placement to timing closure.
Klappentext zu „VLSI Physical Design “
Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact."VLSI Physical Design: From Graph Partitioning to Timing Closure" introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.
Inhaltsverzeichnis zu „VLSI Physical Design “
1 Introduction. 1.1 Electronic Design Automation (EDA). 1.2 VLSI Design Flow. 1.3 VLSI Design Styles. 1.4 Layout Layers and Design Rules. 1.5 Physical Design Optimizations. 1.6 Algorithms and Complexity. 1.7 Graph Theory Terminology. 1.8 Common EDA Terminology. 2 Netlist and System Partitioning. 2.1 Introduction. 2.2 Terminology. 2.3 Optimization Goals. 2.4 Partitioning Algorithms. 2.5 A Framework for Multilevel Partitioning. 2.6 System Partitioning onto Multiple FPGAs. Chapter 2 Exercises.
3 Chip Planning. 3.1 Introduction to Floorplanning. 3.2 Optimization Goals in Floorplanning. 3.3 Terminology. 3.4 Floorplan Representations. 3.5 Floorplanning Algorithms. 3.6 Pin Assignment. 3.7 Power and Ground Routing. Chapter 3 Exercises.
4 Global and Detailed Placement. 4.1 Introduction. 4.2 Optimization Objectives. 4.3 Global Placement. 4.4 Legalization and Detailed Placement. Chapter 4 Exercises.
5 Global Routing. 5.1 Introduction. 5.2 Terminology and Definitions. 5.3 Optimization Goals. 5.4 Representations of Routing Regions. 5.5 The Global Routing Flow. 5.6 Single-Net Routing. 5.7 Full-Netlist Routing. 5.8 Modern Global Routing. Chapter 5 Exercises.
6 Detailed Routing. 6.1 Terminology. 6.2 Horizontal and Vertical Constraint Graphs. 6.3 Channel Routing Algorithms. 6.4 Switchbox Routing. 6.5 Over-the-Cell Routing Algorithms. 6.6 Modern Challenges in Detailed Routing. Chapter 6 Exercises.
7 Specialized Routing. 7.1 Introduction to Area Routing. 7.2 Net Ordering in Area Routing. 7.3 Non-Manhattan Routing. 7.4 Basic Concepts in Clock Networks. 7.5 Modern Clock Tree Synthesis. Chapter 7 Exercises.
8 Timing Closure. 8.1 Introduction. 8.2 Timing Analysis and Performance Constraints. 8.3 Timing-Driven Placement. 8.4 Timing-Driven Routing. 8.5 Physical Synthesis. 8.6 Performance-Driven Design Flow. 8.7 Conclusions. Chapter 8 Exercises.
A Solutions to Chapter Exercises. B Example CMOS Cell Layouts.
Autoren-Porträt von Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Andrew B. Kahng is Professor of CSE and ECE at UC San Diego, where he holds the endowed chair in High-Performance Computing. He has served as visiting scientist at Cadence (1995-1997) and as founder, chairman and CTO at Blaze DFM (2004-2006). Jens Lienig is Professor of Electrical Engineering at TU Dresden. He is also the director of the Institute of Electromechanical and Electronic Design at TUD. He has worked as project manager at Tanner Research, Inc. (1996-1999) and Robert Bosch GmbH (1999-2002).
Igor L. Markov is a Professor of Electrical Engineering and Computer Science at the University of Michigan. He has worked at Google (2014-2017) and has been with Facebook since 2018.
Jin Hu was a PhD student at the Computer Science and Engineering (CSE) Division at the University of Michigan. Afterwards, she has been with IBM Corp. (2013-2017) and Bloomberg L.P.
Bibliographische Angaben
- Autoren: Andrew B. Kahng , Jens Lienig , Igor L. Markov , Jin Hu
- 2011, XI, 310 Seiten, Masse: 16,4 x 24,5 cm, Gebunden, Englisch
- Verlag: Springer Netherlands
- ISBN-10: 904819590X
- ISBN-13: 9789048195909
Sprache:
Englisch
Rezension zu „VLSI Physical Design “
This book covers the basic algorithms underlying all physical design steps and also shows how they are applied to current instances of the design problems. It will serve the EDA and design community well. It will be a foundational text and reference for the next generation of professionals who will be called on to continue the advancement of our chip design tools. Dr. Leon Stok, Vice President, Electronic Design Automation, IBM Systems and Technology Group
Pressezitat
Kommentar zu "VLSI Physical Design"
0 Gebrauchte Artikel zu „VLSI Physical Design“
Zustand | Preis | Porto | Zahlung | Verkäufer | Rating |
---|
Schreiben Sie einen Kommentar zu "VLSI Physical Design".
Kommentar verfassen