Time-interleaved Analog-to-Digital Converters
(Sprache: Englisch)
This book describes the design of a high performance time-interleaved ADC, with much attention given to practical design aspects aimed at both industry and research. There is focus on low-power design techniques including successive approximation ADCs.
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This book describes the design of a high performance time-interleaved ADC, with much attention given to practical design aspects aimed at both industry and research. There is focus on low-power design techniques including successive approximation ADCs.
Klappentext zu „Time-interleaved Analog-to-Digital Converters “
Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration.
The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature.
Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
Inhaltsverzeichnis zu „Time-interleaved Analog-to-Digital Converters “
Preface.1 Introduction. 1.1 Analog-to-digital conversion. 1.2 Architecture. 1.3 Outline.2 Time-interleaved Track and Holds. 2.1 Introduction. 2.2 Mismatch between channels. 2.3 Time-interleaved Track and Hold architectures. 2.4 Track and Hold buffers. 2.5 Bottom-plate sampling in a time-interleaved ADC. 2.6 Number of channels. 2.7 Calibration. 2.8 Jitter requirement on the sample-clock. 2.9 Summary and conclusions.3 Sub-ADC architectures for time-interleaved ADCs. 3.1 Introduction. 3.2 The Successive Approximation ADC. 3.3 Efficiency of SA-ADC versus pipeline ADC. 3.4 Summary and conclusions.4 Implementation of a high-speed time-interleaved ADC. 4.1 Introduction. 4.2 Clock generation. 4.3 Track and Hold. 4.4 Sub-ADC. 4.5 Calibration. 4.6 Layout. 4.7 Measurements. 4.8 Improved design. 4.9 Conclusions.5 Summary and conclusions. 5.1 Summary. 5.2 Conclusions. 5.3 Original contributions. 5.4 Recommendations for future research.About the author. Bibliography. Index. List of Symbols. List of Abbreviations.
Bibliographische Angaben
- Autoren: Simon Louwsma , Ed van Tuijl , Bram Nauta
- 2010, 136 Seiten, Masse: 16,3 x 24,4 cm, Gebunden, Englisch
- Verlag: Springer Netherlands
- ISBN-10: 9048197155
- ISBN-13: 9789048197156
Sprache:
Englisch
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