The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits

Name: The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits
Brand: Springer, Berlin, Springer, Springer US
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The semi-empirical and compact model approaches. Book + Online Access (Sprache: Englisch)

Autor: Paul Jespers

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The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits, Paul Jespers

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Produktinformationen zu „The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits “

In The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits, we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files contained in the CD ROM allow redoing the tests.

Klappentext zu „The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits “

In "The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits", we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com allow redoing the tests.

Inhaltsverzeichnis zu „The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits “

1. Synthesis of the Intrinsic Gain Stage

2. The Charge Sheet Model revisited

3. A graphical representation of the current in MOS transistors

4. The E.K.V. - A.C.M. model

5. Small signal parameters

6. Real transistors

7. Synthesis of Miller Op Amps

8. Synthesis of cascode Op Amps

Autoren-Porträt von Paul Jespers

Dr. Paul Jespers is Professor Emeritus at UCL, Louvain-la-Neuf, Belgium, and has been visiting professor at Stanford ('67-'69) and UC Berkeley ('90-'91).

He has co-authored several books, and in 2001 published "Integrated Digital-to-Analog and Analog-to-Digital Converters" which was published by Wiley (ISBN 0-19-856446-5)

Bibliographische Angaben

Autor: Paul Jespers
2009, XVI, 171 Seiten, Masse: 16,4 x 24,2 cm, Gebunden, Englisch
Verlag: Springer, Berlin
ISBN-10: 0387471006
ISBN-13: 9780387471006

Sprache:

Englisch

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