Quick Start Guide to Verilog

The Modern Digital Design Flow.- Verilog Constructs.- Modeling Concurrent Functionality in Verilog.- Structural Design and Hierarchy.- Modeling Sequential Functionality.- Test Benches.- Modeling Sequential Storage and Registers.- Modeling Finite State Machines.- Modeling Counters.- Modeling Memory.- Computer System Design.

Brock LaMeres joined the Montana State ECE faculty in July of 2006. He received his Ph.D. in electrical engineering from the University of Colorado, Boulder in December of 2005, his MSEE from the University of Colorado, Colorado Springs in May of 2001, and his BSEE from Montana State University, Bozeman in December of 1998. LaMeres teaches and conducts research in the area of digital systems with particular emphasis on exploiting reprogrammable fabrics to deliver more effective computer systems. LaMeres is also studying how engineering education can be improved using innovative e-learning environments.

LaMeres has published over 70 manuscripts and 2 textbooks in the area of high speed digital systems. LaMeres has also been granted 13 US patents in the area of digital signal propagation. LaMeres is a Senior Member of IEEE and a Registered Professional Engineer in the States of Montana and Colorado. Dr. LaMeres is a member of AESS, ASEE and serves as the faculty advisor of the student branch of IEEE at MSU.

Prior to coming to MSU, Dr. LaMeres worked as an R&D engineer for Agilent Technologies in Colorado Springs, CO from 1999 to 2006. LaMeres was a hardware design engineer in the Logic Analysis R&D lab. He designed acquisition hardware for the 16910/11/12 and 16950 Logic Analyzer systems in addition to developing a variety of probing solutions.