Progress in VLSI Design and Test

Reduction of Test Data Volume and Testing Power .-Reusable and Scalable Verification Environment for Memory Controllers.-Design Techniques II Design of a Fault-Tolerant Conditional Sum Adder.-SEU Tolerant Robust Latch Design .-Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect Transistors.-Algorithms and Applications II.-High-Speed Unified Elliptic Curve Cryptosystem on FPGAs Using Binary Huff Curves .-A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology.-VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF (2m) Using Dual Bases .-Emerging Technologies.-A Synthesis Method for Quaternary Quantum Logic Circuits.-On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits.-Delay Uncertainty in Single- and Multi-Wall Carbon Nanotube Interconnects.-Algorithms and Applications III.-A Fast FPGA Based Architecture for Sobel Edge Detection.-Speech Processor Design for Cochlear Implants.-An Efficient Technique for Longest Prefix Matching in Network Routers.-NoC and Physical Design A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts.-Test Data Compression for NoC Based SoCs Using Binary Arithmetic Operations .-Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip.-Poster Presentation An Efficient Multiplexer in Quantum-dot Cellular Automata.-Integrated Placement and Optimization Flow for Structured and Regular Logic.-A Novel Symbol Estimation Algorithm for LTE Standard.-Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance.-A Novel Approach to Voltage-Drop Aware Placement in Large SoCs in Advanced Technology Nodes.-Design and Implementation of Efficient Vedic Multiplier Using Reversible Logic .-Design of Combinational and Sequential Circuits Using Novel Feed through Logic.-Efficient FPGA Implementation of Montgomery Multiplier Using DSP Blocks.-Independent Gate SRAM Based on Asymmetric Gate to Source/Drain Overlap-Underlap Device FinFET.-VLSI Architecture for Spatial Domain Spread Spectrum Image.-Watermarking Using Gray-Scale Watermark .-A Photonic Network on Chip with CDMA Links.-Simulation Study of an Ultra Thin Body Silicon On Insulator Tunnel Field Effect Transistor.-Routing in NoC on Diametrical 2D Mesh Architecture.-Invited Talk Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology (Invited Paper) .-Power Problems in VLSI Circuit Testing.-