Modern Circuit Placement

This book will cover the advanced techniques in placement which is known as one of the most important components of physical design flow in VLSI design. Physical design addresses the back-end layout stage of chip design process. As the technology scales down, the importance of interconnect optimization becomes more important than ever, and physical design, particularly placement process, stands in the center of interconnect optimization.

It will have three unique characteristics compared against other books on design automation or physical design:

1) Focusing solely on most recent placement techniques: The placement process is no longer considered as a point tool within physical design process, particular for timing closure. The industrial trend in physical design is to integrate design optimization techniques such as buffering, gate sizing, or even logic synthesis techniques with placement process. Thus, we cannot overemphasize the important of placement techniques for VLSI timing closure. However, most design automation books allocate one or two chapters for placement only treating the general concepts. Unfortunately, placement has been researched for decades, and most of those concepts are out of date. The purpose of this book is to address all of most recent placement techniques available in the field.

2) Comprehensiveness: Although the book is dedicated to a single topic of placement, the goal of this book is to address all the techniques being used in the field. Recently during ISPD (International Symposium on Physical Design: the conference focusing on physical design process), we had the placement contest where academic placement tools have competed each other on the same industrial benchmark circuits. This book will include all the academic placement tools participated in this contest. Although these are academic placement tools, these techniques are extensively being used in industrial tools too. Thus, it is safe to say that these techniques represents today's advanced placement techniques.

3) (Indirect) comparison among techniques: This book is based on the ISPD placement contest where all these the participating placement tools were run on the same set of industrial benchmark circuits. Therefore, fair comparison can be made among these techniques. The book is expected to provide significant amounts of analysis on each technique such as trade-offs between quality-of-results (QoR) and runtime.

4) Optimality analysis: Recently PEKO synthetic benchmarks drew a lot of attention because they provide the first method to analyze the optimality of placement results. We're going to use the similar benchmarks to analyze the optimality of these placement techniques. As far as we know, this is the almost first time to include the optimality issue of placement techniques in text book.