Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
(Sprache: Englisch)
Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of...
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Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models.
Inhaltsverzeichnis zu „Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms “
- Foreword. Preface1. Introduction
2. Embedded SOC Applications
3. Classification of Platform Elements
4. System Level Design Principles
5. Related Work
6. Methodology Overview
7. Unified Timing Model
8. MP-SOC Simulation Framework
9. Case Study
10. Summary
- Appendices
A: The OSCI TLM Standard
B: The OCPIP TL3 Channel
C: The Architects View Framework
- List of Figures. List of Tables. References
- Index
Bibliographische Angaben
- Autoren: Tim Kogel , Rainer Leupers , Heinrich Meyr
- 2006, 186 Seiten, Masse: 16,5 x 24,8 cm, Gebunden, Englisch
- Verlag: Springer Netherlands
- ISBN-10: 1402048254
- ISBN-13: 9781402048258
- Erscheinungsdatum: 05.07.2006
Sprache:
Englisch
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